This invention relates to a .DELTA..SIGMA. modulation (Delta Sigma modulation) type 1-bit digital-to-analog conversion circuit and a method of the same type having a simplified feedback data computation function and thereby achieving reduction in the computation time.
A 1-bit digital-to-analog conversion circuit (hereinafter abbreviated as "1-bit DAC") converts multibit (e.g., 16-bit) digital data to analog data after requantizing the digital data into 1-bit digital data and thereby attempts, theoretically, to eliminate a zero-cross distortion and a non-linear distortion in the digital-to-analog conversion operation.
In the past, 1-bit DAC has been realized as a .DELTA. modulation (Delta modulation) type 1-bit DAC. In this type of 1-bit DAC, a value obtained by accumulating past data is applied by negative feedback to the input and compared with an input signal. In a case where an input signal is larger than the feedback signal (i.e., difference is a positive value), the output of a 1-bit quantizer which constitutes a comparator becomes "1", whereas in a case where an input signal is smaller than the feedback signal (i.e., difference is a negative value), the output of the 1-bit quantizer becomes "0". The feedback data which is to be compared with next input data increases when the output of the 1-bit quantizer is "1" and it decreases when the output of the 1-bit quantizer is "0". The 1-bit quantizer thereby produces a 1-bit signal corresponding to the difference in the input data and analog data corresponding to input digital data can be obtained by integrating the 1-bit signal by an integrator.
The .DELTA. modulation type 1-bit DAC is simple in its structure but has the disadvantage that a quantizing noise occuring due to requantizing of a 1-bit signal is a white noise which is flat throughout all frequencies with the result that S/N in the audio frequency is deteriorated.
For overcoming this disadvantage, a .DELTA..SIGMA. modulation type (also called a "noise-shaping" type) 1-bit DAC has been developed as a system according to which a quantizing noise in low frequencies is shifted to high frequencies and S/N in the audio frequency thereby is improved. According to this noise shaping technique, low frequency boosting is made before quantizing of data and low frequency cutting is made after quantizing of the data whereby a quantizing noise in low frequencies is reduced without changing the frequency-response characteristic of the data.
The basic structure of a secondary .DELTA..SIGMA. modulation type 1-bit DAC is shown in FIG. 2. An input multi-bit (e.g., 16-bit) digital signal X is applied to an adder 11 which produces a difference signal representing a difference between the input signal X and a signal obtained by delaying an output of a 1-bit quantizer 10 by a 1-sample delay circuit 16. This difference signal is integrated by a first integration circuit 20 which is composed of an adder 12 and a 1-sample delay circuit 18.
The output of the first integration circuit 20 is applied to an adder 13 which produces a difference signal representing a difference between the output of the first integration circuit and the output of the 1-sample delay circuit 16. This difference signal is integrated by a second integration circuit 28 which is composed of an adder 14 and a delay circuit 26.
The output of the second integration circuit 28 is applied to a 1-bit quantizer 10. This 1-bit quantizer 10 consists of a zero-cross comparator and produces binary outputs (i.e., either a positive maximum value or a negative maximum value is provided.) in accordance with the polarity of the output of the second integration circuit 28. This output of the 1-bit quantizer 10 constitutes a 1-bit quantizing output Y.
It is a condition for working of the secondary .DELTA..SIGMA. type 1-bit DAC shown in FIG. 2 that the entire processings of the adders 11 to 14 must be completed within 1 output sample time of the output Y.
In additions in the adders 11 to 14, however, processing of higher order bits cannot be made unless presence or absence of carry from lower order bits is known and, accordingly, each of these additions requires a processing time corresponding to the number of bits of the data. In a 16-bit 2's complement code used in digital audio systems such as the Compact Disc Digital Audio System (CD) and digital audio tape recorders (DAT), for example, an input signal consists of 16 bit data and a feedback signal consists of 16 bit data with its positive maximum value being EQU 0111 1111 1111 1111
(i.e., 7FFF .sub.H in hexadecimal notation) and its negative maximum value being EQU 1000 0000 0000 0001
(i.e., 8001 .sub.H in hexadecimal notation).
A single addition in the prior art 1-bit DAC, therefore, requires a processing time which is sixteen times as long as that for completing one arithmetic operation for one of 16 bit code. Moreover, since the adders 11 to 14 are serially connected, a processing time which is four times as long as that for a single addition, i.e., sixty-four times as long as that for completing one arithmetic operation as a whole, is required. Accordingly, if the bit number of data is increased (e.g., 20 bits) or the sampling frequency is increased (e.g., over 10 MHz), it will become extremely difficult to complete all of the additions in the adders 11 to 14 within 1 output sample time of the output Y.
It is, therefore, an object of the invention to provide a 1-bit DAC which is simplified in its computation of feedback data to shorten time required for computation of the feedback data and thereby is capable of coping with increase in the bit number of input data or increase in the sampling frequency.